By Rainer Leupers
The construction blocks of latest and destiny embedded platforms are advanced highbrow estate parts, or cores, lots of that are programmable processors. typically, those embedded processors ordinarily were seasoned grammed in meeting languages as a result of potency purposes. this means time eating programming, vast debugging, and occasional code portability. the necessities of brief time-to-market and dependability of embedded platforms are patently far better met by utilizing high-level language (e.g. C) compil ers rather than meeting. besides the fact that, using C compilers usually incurs a code caliber overhead compared to manually written meeting courses. end result of the want for effective embedded platforms, this overhead needs to be very low so one can make compilers precious in perform. In flip, this calls for new compiler suggestions that take the categorical constraints in embedded procedure de signal under consideration. An instance are the really good architectures of contemporary DSP and multimedia processors, which aren't but sufficiently exploited via current compilers.
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Additional resources for Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools
ASM96], who presented a graph-based discussion. We will also concentrate on array index expressions of the form "i ± c" for some loop variable i and some constant c. g. for multi-dimensional arrays, can mostly be transformed into this simple form by standard induction variable elimination techniques [ASU86]. 17. Addressing with seven ARs algorithm for optimized array index allocation. This technique will be presented in more detail in the next section. A different approach has been taken in [Gebo97a], where also physical AR limits have been incorporated into array index allocation.
However, the exploitation of MRs requires additional effort. As described in [LeMa96b ], we can use a variant of a page replacement algorithm in order to optimally exploit m MRs for a given offset assignment, which we briefly summarize here. Any offset assignment is characterized by a sequence of modify values (d1, .. , dm-d· A value di denotes that an AR needs to be incremented (or decremented) by di in order to compute the memory address required for variable access Si· Any di less or equal tor can be implemented by auto-increment and thus does not incur costs.
The access sequence is B[i] a2 : B[i + 1] a3 : B[i] a4: B[i + 1] a1 : Memory Address Computation for DSPs 47 One obvious way to allocate ARs to the accesses would be to use one pointer p 1 for a 1 and a3 and another pointer p 2 for a2 and a4 • The pointers are initialized with &B  and &B , respectively, and both need to be incremented by 2 at the end of each iteration in order to point to the correct data pair in the next iteration. If we want to optimize for performance, we may neglect the initialization cost and focus on the cost of address computations inside the loop body.