By Bart Vermeulen, Kees Goossens (auth.)
This publication describes an strategy and helping infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), permitting its linked product to be brought into the marketplace extra speedy. Readers study step by step the main standards for debugging a latest, silicon SOC implementation, 9 elements that complicate this debugging job, and a brand new debug technique that addresses those standards and complicating elements. The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug technique is mentioned intimately, displaying the way it is helping to fulfill debug standards and tackle the 9, formerly pointed out elements that complicate debugging silicon implementations of SOCs. The authors additionally derive the debug infrastructure necessities to help debugging of a silicon implementation of an SOC with their CSAR debug technique. This debug infrastructure contains a well-known on-chip debug structure, a configurable automatic design-for-debug stream for use through the layout of an SOC, and customizable off-chip debugger software program. assurance comprises an assessment of the potency and effectiveness of the CSAR technique and its assisting infrastructure, utilizing six business SOCs and an illustrative, instance SOC version. The authors additionally quantify the expense and layout attempt to help their approach.
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Additional info for Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques
In the ideal debug experiment, we can observe the behavior of an implementation in every detail and at every point during its execution. We use this observability to quickly find the location inside the implementation and the earliest point in time at which the behavior of the implementation deviates from the behavior of the reference. However, in an actual debug experiment the means by which we can observe the behavior of a silicon implementation are both spatially and temporally severely restricted.
A block diagram of an FSM is shown in Fig. 1. The FSM in Fig. 1 has an input I , an internal state s, and an output O. The input I takes a value from the set I with a possible input symbols. The state takes its value from the set S with b possible states. The output O takes its value from the set O with c possible output symbols. The current state s of the FSM is stored in a register, which is triggered by the input clock signal “clk”. The content of this register is set to the output of the combinational logic block δ, whenever a rising edge occurs on this clock signal.
Before then, we first investigate the factors that complicate the debugging of multiple, interacting building blocks in the next chapter, because SOC are composed of multiple building blocks. References 1. John E. Hopcroft and Jeffrey D. Ullman. Introduction To Automata Theory, Languages, And Computation. , 1979. 2. George H. Mealy. A method for synthesizing sequential circuits. Bell Systems Technical Journal, 34:1045–1079, September 1955. 3. Edward F Moore. Gedanken-experiments on sequential machines.