By Baker Mohammad
This publication describes a few of the tradeoffs structures designers face while designing embedded reminiscence. Readers designing multi-core structures and structures on chip will enjoy the dialogue of other themes from reminiscence structure, array association, circuit layout ideas and layout for try out. The presentation allows a multi-disciplinary method of chip layout, which bridges the distance among the structure point and circuit point, so one can handle yield, reliability and power-related concerns for embedded reminiscence.
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Additional resources for Embedded Memory Design for Multi-Core and Systems on Chip
In addition to these factors, controlling variability through process technology further reduces the device parameter shift. The SRAM cell stability and its effect on both yield and power have been addressed through several techniques, and they are as follows: 1. 2. 3. 4. 5. Process technology and transistor sizing SRAM cell modification Voltage islands Body/well biasing Circuit techniques, often referred, to as assist circuits Each of the above techniques targets one or more factors to reduce the impact of cell stability on the overall power and yield.
On the other hand, a singleissue general-purpose processor will have less activity on the PA bus, which makes the CAM-based tag more power-efficient. 5 Summary Tag Selection Deciding on the tag array used in the memory subsystem has significant implications on power, area, and speed. In our analysis, we showed that CAM-based tags always are larger in area (constituting about 10–20 % of the total cache). Since memory subsystems constitute more than 50 % of the area in modern processors, this characteristic makes the CAM-based tag area overhead to the total processor area between 5 and 10 %.
Fig. 2 Memory hierarchy for multi-core  32 3 Embedded Memory Hierarchy Fig. 3 Die photo of high-end z-processor showing memory hierarchy  As for cost different technology provides tradeoffs, for example eDRAM added masks to normal CMOS to realize trench capacitance. The additional cost associated with the eDRAM masks has to be offsetted by the area saving from using eDRAM versus SRAM. The memory size has to be big enough to make up for cost and it is estimated to be greater than 4 MB at 45 nm technology.