By Günter Böckle
ISBN-10: 354060054X
ISBN-13: 9783540600541
Many parallel desktop architectures are specially suited to specific sessions of functions. even though, there are just a few parallel architectures both well matched for traditional courses. a lot attempt is invested into examine in compiler concepts to make programming parallel machines easier.
This booklet provides equipment for computerized parallelization, in order that courses needn't to be adapted for particular architectures; the following the point of interest is on fine-grain parallelism, provided by way of such a lot new microprocessor architectures. The e-book addresses compiler writers, machine architects, and scholars through demonstrating the manifold complicated relationships among structure and compiler technology.
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Extra info for Exploitation of Fine-Grain Parallelism
Example text
This mechanism supports the conditional execution model. The branch conditions are represented as expressions of the contents of the 8 condition-code registers. For each conditional-branch operation in the instruction Iree there are two 8-bit masks to code these expressions, for the TRUE-path and the FALSEpath, respectively. These masks specify two subsets of the set of condition-code registers; condition-code register i belongs to the first subset if the i-th bit of the first mask is set. The branch condition evaluates to TRUE if all condition-code registers specified by the first of these sets are TRUE, and all condition-code registers of the second set contain the value FALSE (compare figure 21 and the expressions thereafter on page 48).
The performance degradation caused by this pipeline stall can be avoided ff the machine operation following the branch is always executed, independent of the branch's condition. e. if the condition evaluates to FALSE); in the TRUE-case this operation is not intended to be executed. Thus, if the variable produced by this operation is used in the TRUE successor path, it will contain an incorrect value, let's have a look at an example: The instruction sequence on the left is transformed to the symbolic machine instructions on the right: a = 5; a = 5; ff (x < O) then { a=a- jump_ff_greater_O x, L1; 1; a=a- b=4; } 1; b=4; else jump L2; {a=a+l; LI: a = a + l ; b = 12; ] a r {4,6} b = 12; L2: ...
In applications with many branch and call operations, VLIW architectures are limited in their capability to exploit enough parallelism; this holds still more for superscalar architectures. Multiway branches are quite complex to implement and thus the number of branches which can be executed concurrently is limited. Unpredictable memory and peripherals behaviour may decrease performance because a parallelizing compiler has to make worst-case assumptions to guarantee correct program execution. The XIMD architecture (an acronym for Variable Instruction Stream, Multiple Data Stream Processor) combines the idea of instruction streams with VLIW by controlling each proeessing unit by a separate program counter.