By J. C. Cluley (auth.)
ISBN-10: 0333340612
ISBN-13: 9780333340615
ISBN-10: 1349064971
ISBN-13: 9781349064977
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Example text
The two IRQ lines are open-drain outputs, active low, and are usually both connected to the processor IRQ line. If fast interrupt handling and priority arbitration is important, they can be taken separately to a priority arbitration package. This assesses the highest priority request and sends its vector address from a small ROM to the processor. For smaller systems the most important line could be connected to the NMI input which the processor treats as higher priority than the IRQ line. The external connections to the PIA are PAO-PA7 CAl, CA2 PBO-PB7 CBl, CB2 8 data lines, port A control lines, port A 8 data lines, port B control lines, port B The data lines have bistables driving them when they are programmed as outputs, so that data, once written to them by the processor, are stored unchanged until altered by the next write operation.
It then samples the input again after half a bit period, which should occur in the middle of the start bit. If the input is still space, the receiver accepts it as a genuine starting bit, and samples the remainder of the character in the middle of each bit period. Thus the receiving clock signal must keep in synchronism with the transmitting clock only for the fraction of a second needed for sending a complete character. This protocol was developed for mechanical teleprinters which were governed in speed by centrifugal governors.
The value of N determines which vector address the processor selects from which to start the service routine. The options are as follows N Address (hexadecimal) 0 00 08 2 3 4 5 6 7 10 18 20 28 30 38 This operation code is carefully chosen; the data lines are normally connected to +5 V via 'pull-up' resistors of 3-10 kQ. Thus only those bits of N which have value 0 need driving circuits connected to the data bus. For example for N = 2 (010 binary), D3 = 0, DS = 0, and all other bits of the restart instruction are 1.