By Andy C. Downton
ISBN-10: 0471388602
ISBN-13: 9780471388609
This publication outlines a technique for using parallel processing in genuine time platforms. It presents an creation to parallel processing commonly, and to embedded platforms particularly. one of the embedded platforms are processors in such functions as autos, a variety of equipment, IPGAs (field programmable gate arrays), multimedia embedded structures akin to these utilized in the pc online game undefined, and extra. * provides layout and simulation instruments in addition to case reports. * First presentation of this fabric in publication shape.
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Additional info for Pipelined Processor Farms - Structured Design for Embedded Parallel Systems
Sample text
A further assumption was that task duration times are deterministic. However in [373], varying task durations were represented by mean values but the linear-programming technique was retained. Maximum performance was more closely estimated by including a number of overhead terms. In one version of the scheme [338], tasks were placed on workers in advance as if the 28 BASIC CONCEPTS distribution of tasks had been formed by demand-based farming. In theory, task granularity can be found by optimizing the governing equations for the model.
A simple pipeline is defined as one in which a single processor appears at each stage. This structure is now analyzed more formally to identify its mathematical characteristics. Fig. la showsjust one global maximum latency time though there might be a finite number of local maxima. It is the global maximum and its stage index that are of interest. Formally, T 77lUX e bnax = = max({T(i),i argmin(l‘,,, = 1,2,. . 2) 26 BASK CONCEPTS with {T(i)} being the set of maximum per-stage latencies and s being the number of stages.
The first equation defines this casewhere the performance is increasing linearly as the number of workers in the processor farm increases (S is proportional to n); this continues until the execution time for the processor farm drops below that of the next slowest stage, T3 in this case. The second equation then defines the fixed scaling achieved for any further increase in processor numbers (S is fixed and independent of n). t 4 -3 -2 -1 dP 01 1 I I I I I I I I I I I I I I I I I I I I I I I I I 2 3 4 5 6 7 8 9 10 11 12 13 14 Nuder Fig.