By Yu Hen Hu
ISBN-10: 058540402X
ISBN-13: 9780585404028
ISBN-10: 0824706471
ISBN-13: 9780824706470
ISBN-10: 0824741544
ISBN-13: 9780824741549
Offers the newest advancements within the prgramming and layout of programmable electronic sign processors (PDSPs) with very-long-instruction be aware (VLIW) structure, set of rules formula and implementation, and smooth purposes for multimedia processing, communications, and business keep an eye on.
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Extra resources for Programmable digital signal processors: architecture, programming, and applications
Example text
A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 20 A 21 A 22 A 23 A 24 A 25 A 26 A 27 A 30 A 31 A 32 A 33 A 34 A 35 A 36 A 37 A 40 A 41 A 42 A 43 A 44 A 45 A 46 A 47 A 50 A 51 A 52 A 53 A 54 A 55 A 56 A 57 A 60 A 61 A 62 A 63 A 64 A 65 A 66 A 67 A 70 A 71 A 72 A 73 A 74 A 75 A 76 A 77 ϫ F0 F1 F2 F3 F4 F5 F6 F7 as a product between the basis matrix A and the input vector F. ps16 instruction that can perform eight 16bit multiplications and accumulate the results with a single-cycle throughput, only one instruction is necessary to compute one output element f x : 7 fx ϭ ΑA ux Fu uϭ0 This instruction utilizes 128-bit PLC and PLV registers.
25), the DMA controller can be programmed to write zeros in the output image block directly without bringing any input pixels on-chip. If the bounding block is partially filled (case 2), then the DMA controller can be programmed to bring only valid input pixels on-chip and fill the rest of the output image block with zeros. If the bounding block is completely filled with valid input pixels (case 1), the whole block is brought on-chip using the DMA controller. In addition, these data movements are double buffered so that the data transfer time can be overlapped with the processing time.
The key idea shared by all of these extensions to achieve this goal is the use of subword parallelism. The instructions included in the extensions are commonly based on operating in parallel on packed data types. As we will address in the following sections, significant differences exist among different ISAs and extensions, in the types and the sizes of the subwords, as well as for the support provided for these subwords. 2 A Note on Instruction Formatting Throughout this chapter, we assume that all the instructions (with the possible exclusion of loads and stores) use registers for operand and target fields.