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4 provides a more detailed view of the chip integration process. The role of each element is described below. Executable Specification An executable specification is the chip or product requirements captured in terms of explicit functionality and performance criteria. These can be translated into constraints for the rest of the design process. Traditionally, the specification is a paper document, however, by capturing the specification as a formal set of design objectives, using simulatable, high-level models with abstract data types and key metrics for the design performance, the specification can be used in an interactive manner for evaluating the appropriateness of the specification itself and testing against downstream implementation choices.

These divisions are based on many factors, including performance requirements, ease of design and implementation, resource allocation, and cost. The partitions can be across hardware/software, hardware/hardware, and software/software. Systems analysis and performance simulation can facilitate this step. Interface Definition Once the functional elements, or modules/blocks, have been partitioned, the next step is to define the appropriate interfaces and interface dependencies between the elements.

Planning considers and assigns, as needed, I/O locations, subblock placement, and logic to regions of the block. It eventually directs placement of all cells in the target or reference technology. It invokes a variety of specific layout functions, including constraint refinement, synthesis or custom design, placement, clock tree, power, and test logic generation. Fundamentally, the power of the planner lies in its ability to accurately predict the downstream implementation results and then to manage the interconnect through constraints to synthesis, placement, and routing.