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The order of statements in this section is not important and all statements are sensitive to their sensitivity list, meaning that they execute when an event occurs on any of their right-hand side signals. Sensitivity lists are discussed further on. 5 Shift-register. Another structure that is used as a data component is a register with or without various shift capabilities. Here we show a shift-register with two mode inputs m[1:0] that form a 2-bit number. When m is 0, the shifter does nothing (retains its old value), for values of m = 1 and m = 2 it shifts its contents right and left, respectively, and for m = 3 it loads its parallel inputs into the register.

This example has shown how timing is used in a procedural body of Verilog. Procedural bodies are used for description of testbenches or for describing a hardware component whose behavior is too complex to be described with simple boolean equations. 2 Full adder Tester Procedural Description Module Basics The previous section discussed some of the main concepts of the Verilog language. To prepare for description of hardware, this section shows how modules are developed, and how names, numbers, and operators are used.

In our examples, we use bold type for Verilog codes for keywords. System tasks and functions are part of the Verilog standard. The names of these utilities begin with a $ character. An example system task is $display, which is used for formatted output. System tasks and functions will be discussed later in this chapter. The Verilog language defines a number of compiler directives that will be discussed later. Compiler directive names are preceded by the ` (back single quote) character. An example is the `timescale directive, which defines the time unit for a Verilog code in a source text.