By Ulrich Golze
ISBN-10: 3642610013
ISBN-13: 9783642610011
ISBN-10: 3642646506
ISBN-13: 9783642646508
This e-book introduces to fashionable layout of enormous chips. a strong RISC processor within the diversity of a SPARC is apecified in a description language (HDL), it truly is built hierarchically and is eventually despatched as a gate version to the silicon seller LSI good judgment for creation. The ensuing processor on a semi-custom gate-array chip with greater than 50.000 used gates and an potency of as much as forty MIPS is confirmed on an automated attempt gear and a testboard. The ebook additionally introduces completely to the HDL VERILOG. The incorporated disk includes greater than forty small and medium sized executable VERILOG examples, the massive processor types and the VERILOG simulator VeriWell operating on workstation or SPARC.
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Additional info for VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design
Sample text
There are two module types one _ bit _ adde r and four _ bi t _adder. Signals CARRY_OUT and SUM are concatenated by { and } to form a new 2-bit variable. The sum of A, B, and CARRY_IN is assigned in an a 1 way s loop to this composition as soon as one of the three variables changes. The four _ bi t _adder implements the addition of two 4-bit variables by four instances of the one _ bi t _adder. A result of width 5 is generated, and a flag is set, if the result is O. In lines 30 and 31, another module nor is instantiated which is predefined in VERILOG.
The following basic RISe features should be considered in parallel, as they all depend upon each other. Not all features are found in every RISe computer. Many of them are worked out in the following chapters. 1. Few simple instructions. This feature indicated by the name RISe allows efficient pipelining (features 4 and 6). Based on statistical analysis, only frequently needed instructions are implemented, the others will be synthesized by the compiler. This and the reduction of pipeline hazards (5) like data dependency or branch problems favor adapted compilers and special hardware.
This board can be designed in parallel to processor design (Chapter 9). The testboard is a simple single-board computer with TOOBSIE as CPU. In addition, there are a PC interface and a static RAM system with memory logic. A PC is connected to the testboard to serve as a power supply and for memory initialization. After the program loading TOOBSIE is started. During and after its execution, the memory contents are read and evaluated by the PC. The board is characterized by a flexible timing, a flexible memory protocol, and a not yet specified pin assignment of the processor chip.