Download Offset Reduction Techniques in High-Speed Analog-To-Digital by Pedro M. Figueiredo PDF

By Pedro M. Figueiredo

ISBN-10: 1402097158

ISBN-13: 9781402097157

ISBN-10: 1402097166

ISBN-13: 9781402097164

Offset aid innovations in High-Speed Analog-to-Digital Converters analyzes, describes the layout, and provides try result of Analog-to-Digital Converters (ADCs) applying the 3 major high-speed architectures: flash, two-step flash and folding and interpolation. the benefits and obstacles of every one are reviewed, and the innovations hired to enhance their functionality are mentioned.

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Extra info for Offset Reduction Techniques in High-Speed Analog-To-Digital Converters Analysis Design and Tradeoff

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Furthermore the bandwidth of the folding circuits is also smaller due to the presence of several differential pairs connected to the output nodes, instead of a single one. Chapter 1: High-Speed ADC Architectures 39 and vGS is the gate-to-source voltage, Vt is the threshold voltage, μ is the carrier mobility, Cox is the gate capacitance per unit of area and W and L are the gate dimensions of the transistor. 28. Differential pair with NMOS transistors. Analyzing the differential pair of Fig. 28 leads to β 2 iDP = (vGSP −Vt ) , 2 β 2 iDN = (vGSN −Vt ) , 2 iDP + iDN = I SS , vD = vGSN − vGSP .

4, where the termination of averaged folding circuits is addressed. Offset Reduction Techniques in High-Speed ADCs 30 Examining the outputs of the latched comparators connected to the folding and interpolation circuits one finds a circular code, as depicted in Fig. 21. This code repeats itself in each folding period. 21. Circular code (example for FB = 4 and no interpolation). 3, the folding circuit most widely used in CMOS data converters is composed by FF differential pairs, having the following practical limitations to the maximum folding factor that can be implemented: „ „ The load capacitance rises with FF, due to the increasing number of differential pairs connected to the output nodes.

34) VOVD The gain is, therefore, the ratio between the output voltage range, ISSR0, and the overdrive voltage of the transistors. 35) where CL includes the drain capacitance of transistors, the input capacitance of the next stage and the parasitic capacitance of the metal connections. The drain capacitance of the MOS transistors is composed by the drain-to-bulk capacitance, CDB, and the gate-to-drain capacitance, CGD. CDB is the depletion capacitance of the pn junction formed by the drain and the substrate, and CGD results from the small overlap existing between the gate and the drain – both are proportional to W [91].

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