By Francky Catthoor, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Angeliki Kritikakou, Javed Absar
ISBN-10: 9048195276
ISBN-13: 9789048195275
Modern shoppers hold many digital units, like a cellular phone, digicam, GPS, PDA and an MP3 participant. The performance of every of those units has passed through a big evolution over contemporary years, with a steep raise in either the variety of positive factors as within the caliber of the companies that they supply. in spite of the fact that, offering the mandatory compute strength to help (an uncompromised mixture of) all this performance is very non-trivial. Designing processors that meet the difficult requisites of destiny cellular units calls for the optimization of the embedded process usually and of the embedded processors particularly, as they need to strike the proper stability among flexibility, strength potency and function. typically, a fashion designer will try and reduce the strength intake (as some distance as wanted) for a given functionality, with a adequate flexibility. even if, attaining this target is already advanced while the processor in isolation, yet, actually, the processor is a unmarried part in a extra advanced method. on the way to layout such advanced method effectively, severe judgements throughout the layout of every person part may still bear in mind impact at the different elements, with a transparent target to maneuver to an international Pareto optimal within the entire multi-dimensional exploration space.
In the advanced, worldwide layout of battery-operated embedded platforms, the focal point of Ultra-Low power Domain-Specific Instruction-Set Processors is at the energy-aware structure exploration of domain-specific instruction-set processors and the co-optimization of the datapath structure, foreground reminiscence, and guide reminiscence employer with a hyperlink to the necessary mapping strategies or compiler steps on the early levels of the layout. by means of appearing an in depth power breakdown test for an entire embedded platform, either strength and function bottlenecks were pointed out, including the real kin among the several elements. in keeping with this data, structure extensions are proposed for the entire bottlenecks.
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Extra info for Ultra-Low Energy Domain-Specific Instruction-Set Processors
Sample text
At the lowest performance and lowest flexibility side of the processor spectrum, ultra-low power micro-controllers, like TI’s MSP430 [TI09a] can be used to do very basic types of processing. They are good candidates when the total energy budget is extremely constrained and when the workload and performance requirements are correspondingly low. They are namely optimized mostly for control tasks. g. [ARM09a]. They are typically small in-order single slot machines that have a shallow pipeline and that can exploit only a limited amount of parallelism.
Vector register files [Kap03, Asa98, Koz03] target data paths that provide data level parallelism (SIMD) and form another important class of foreground memory. For each of these architectures a range of register allocation techniques exist [Zha02, Smi04, Cha82]. Some techniques like [Das06] target specific streaming models of register file as well. In addition to the register file and the datapath, most state-of-the-art processors have special forwarding paths between the functional units. This allows more flexibility as data can be sent from one FU to another without passing through the register file [Gan07, Sch07].
On further refinement, architectures can also be evaluated/explored at Register Transfer Level (RTL). This is very time consuming and often only minor modifications are done during exploration at RTL level at the complete processor level. This can then be refined to gate level and simulated as well. Both RTL and gate level simulation for multi-million gate designs are prohibitively slow and therefore are not usable. However, instead of simulating the gate level model, it can also be mapped on an FPGA.