By Yoshio Nishi, Robert Doering
ISBN-10: 1574446754
ISBN-13: 9781574446753
Keeping the excellent and in-depth technique that cemented the bestselling first edition's position as a customary reference within the box, the guide of Semiconductor production know-how, moment variation positive aspects new and up to date fabric that retains it on the forefront of modern such a lot dynamic and speedily growing to be box. Iconic specialists Robert Doering and Yoshio Nishi have back assembled a group of the world's major experts in each quarter of semiconductor production to supply the main trustworthy, authoritative, and industry-leading details available.
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In addition to updates to just about each latest bankruptcy, this variation gains 5 completely new contributions on…
Reflecting quick development in lots of components, a number of chapters have been seriously revised and up-to-date, and every so often, rewritten to mirror quick advances in such parts as interconnect applied sciences, gate dielectrics, photomask fabrication, IC packaging, and three hundred mm wafer fabrication.
While no ebook will be up to date with the advances within the semiconductor box, the guide of Semiconductor production know-how retains an important info, tools, instruments, and methods shut at hand.
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Additional info for Handbook of Semiconductor Manufacturing Technology, Second Edition
Sample text
This has been used by the industry during the golden era of scaling to not only increase the packing density and functionality, but also to rapidly increase the clock frequency of microprocessors by many factors of 2. The projected scaling in the 2004 ITRS makes it considerably more difficult to continue decreasing the gate delay. This arises because the highly desired decrease in logic voltage level has been considerably slowed. 8 shows that the decrease has changed to about 15% per technology generation rather than the previous 30% per generation.
For the purposes of proper circuit operation and power management, these parasitic and undesirable currents must be kept below some upper limit. Static off-state power dissipation can be expressed as poff Z VDD Id;leak ð1:22Þ Limits for the allowable leakage current comes not from the fundamental device limits, but from circuit and system limits on the allowable values of static off power that can be managed in a given IC application. In general, one desires a low value of off-to-on state leakage current.
Some preliminary data on the reliability of high-k dielectrics has been encouraging, and it may in fact be possible to increase the effective dielectric field as proposed in the ITRS without degrading long-term device lifetime. As this is written, there are still DK4126—Chapter1—23/5/2007—18:33—ANBARASAN—240430—XML MODEL CRC12a – pp. 5-nm range. In addition to the gate insulator, the gate contact is a critical part of the gate stack. This has typically been polysilicon and more typically both nC and pC polysilicon for n- and p-channel devices, respectively.