By Pedro M. Figueiredo
ISBN-10: 1402097158
ISBN-13: 9781402097157
Offset aid recommendations in High-Speed Analog-to-Digital Converters analyzes, describes the layout, and provides attempt result of Analog-to-Digital Converters (ADCs) applying the 3 major high-speed architectures: flash, two-step flash and folding and interpolation. the benefits and obstacles of every one are reviewed, and the options hired to enhance their functionality are mentioned.
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Extra resources for Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs
Example text
This tradeoff can be relaxed by using offset reduction techniques: offset sampling [11, 29–35] and averaging [28, 36]. The averaging technique was proposed in [36] and is now commonly employed in high speed flash ADCs [24–27, 37]. It consists in the connection of low value resistors between the outputs of the pre-amplifiers, which correlates their output voltages. Each code transition level is defined by a weighted sum (average) of the random deviations in the elements of many pre-amplifiers, which effectively lowers the offset voltages.
26. Illustration of the output voltages of the S/H and folding stages (NFstg = 2), when the pipelined folding technique is used. Another technique, which was proposed in [84] and more recently used in [88], is particularly well adapted to the notion that only the zero crossings are relevant. 27 shows the output signals of the various blocks when this technique is used. In the previous examples the input signal was applied to a S/H, whose output voltage is zero during half clock period (reset phase), and settles to the sampled value during the other half clock period (amplification phase).
This technique can also be used to obtain extra folding characteristics and decrease the number of necessary folding circuits (Fig. 17). The total number of zeros crossings generated in this way, NTOT, is NTOT = FFFBIF. 14) The distance between zeros of consecutive folding circuits, ΔVB, is ΔVB = vO ΔVF = I FVLSB . 17. Transfer function of two consecutive folding circuits, and the characteristics obtained by interpolation (FF = 5 and IF = 4). All converters employing folding also use interpolation – for this reason they are called folding and interpolation ADCs.